PIC18F1230T-I/SO【PDF 50/318 页】IC PIC MCU FLASH 2KX16 18SOIC

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PIC18F1230/1330

2009 Microchip Technology Inc.

DS39758D-page 143

14.12.2

FAULT INPUT MODE

The FLTAMOD bit in the FLTCONFIG register

determines whether the PWM I/O pins are deactivated

when they are overridden by a Fault input.

FLTAS bit in the FLTCONFIG register gives the status

of the Fault A input.

The Fault input has two modes of operation:

Inactive Mode (FLTAMOD = 0)

This is a catastrophic Fault Management mode.

When the Fault occurs in this mode, the PWM

outputs are deactivated. The PWM pins will remain in

Inactivated mode until the Fault is cleared (Fault

input is driven high) and the corresponding Fault

status bit has been cleared in software. The PWM

outputs are enabled immediately at the beginning of

the following PWM period, after Fault status bit

(FLTAS) is cleared.

Cycle-by-Cycle Mode (FLTAMOD = 1)

When the Fault occurs in this mode, the PWM

outputs are deactivated. The PWM outputs will

remain in the defined Fault states (all PWM outputs

inactive) for as long as the Fault pin is held low. After

the Fault pin is driven high, the PWM outputs will

return to normal operation at the beginning of the

following PWM period and the FLTAS bit is

automatically cleared.

14.12.3

PWM OUTPUTS WHILE IN FAULT

CONDITION

While in the Fault state (i.e., FLTA input is active), the

PWM output signals are driven into their inactive

states.

14.12.4

PWM OUTPUTS IN DEBUG MODE

The BRFEN bit in the FLTCONFIG register controls the

simulation of Fault condition when a breakpoint is hit,

while debugging the application using an In-Circuit

Debugger (ICD). Setting the BRFEN bit to high enables

the Fault condition on breakpoint, thus driving the PWM

outputs to inactive state. This is done to avoid any

continuous keeping of status on the PWM pin, which

may result in damage of the power devices connected

to the PWM outputs.

If BRFEN = 0, the Fault condition on breakpoint is

disabled.

Note:

It is highly recommended to enable the

Fault condition on breakpoint if a

debugging tool is used while developing

the firmware and the high-power circuitry

is used. When the device is ready to

program after debugging the firmware, the

BRFEN bit can be disabled.

REGISTER 14-8:

FLTCONFIG: FAULT CONFIGURATION REGISTER

R/W-0

U-0

R/W-0

BRFEN

—

FLTAS

FLTAMOD

FLTAEN

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

BRFEN:

Breakpoint Fault Enable bit

= Enable Fault condition on a breakpoint

= Disable Fault condition

bit 6-3

Unimplemented:

Read as ‘0’

bit 2

FLTAS:

Fault A Status bit

=FLTA is asserted:

if FLTAMOD = 0, cleared by the user;

if FLTAMOD = 1, cleared automatically at beginning of the new period when FLTA is deasserted

=No Fault

bit 1

FLTAMOD:

Fault A Mode bit

= Cycle-by-Cycle mode: Pins are inactive for the remainder of the current PWM period or until FLTA

is deasserted; FLTAS is cleared automatically

= Inactive mode: Pins are deactivated (catastrophic failure) until FLTA is deasserted and FLTAS is

cleared by the user only

bit 0

FLTAEN:

Fault A Enable bit

= Enable Fault A

= Disable Fault A

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